Method of fabricating a semiconductor interconnect structure

ABSTRACT

A method for forming a semiconductor interconnect structure includes forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening therein. A metal layer fills the opening and covers the dielectric layer. The metal layer is planarized so that it is co-planar with a top of the dielectric layer. A treating process is performed on the metal layer to convert a top surface thereof into a metal oxide layer. A copper-containing layer is then formed over the metal oxide layer and the dielectric layer. The copper-containing layer is etched to form interconnect features, wherein the etching stops at the metal oxide layer and does not etch into the underlying metal layer. A radiation exposure process is thereafter performed on the metal oxide layer to convert it into a non-oxidized metal layer.

RELATED CASES

This application is a continuation of U.S. patent application Ser. No.13/901,340, filed May 23, 2013, and entitled, “Method of Fabricating aSemiconductor Interconnect Structure,” which application claims priorityto U.S. Provisional Patent Application No. 61/783,944, filed Mar. 14,2013, entitled “Conductive Structure Recess Free Process and StructureFormed Thereby,” both of which applications are incorporated herein byreference.

BACKGROUND

Since the mid-1990's so-called damascene processes have been thedominant technology for forming conductive interconnects in integratedcircuits. Those skilled in the art recognize that damascene processinginvolves forming openings (via and trenches) in a dielectric layer andthen filling the openings with a conductive, typically copper. Thecopper is typically deposited by initially depositing a thin seed layerwithin the openings and then filling the openings by electroplatingcopper.

FIG. 1 is a cross-sectional view of an interconnect formed on asemiconductor device from the prior art. In the figure, a patterneddielectric layer 54 is formed on a substrate 50. Formed between anopening of the patterned dielectric layer 54 and thereabove is aconductive layer 58. Formed between the dielectric layer 54 and theconductive layer 58 is a hard mask 56. A mask layer, such as a tri-layerphotoresist layer 60 is formed above the conductive layer 58. In a laterprocess, using the tri-layer photoresist layer 60 as a mask, theconductive layer 58 will be etched to form conductive lines 58 above thedielectric layer 54, as shown in FIG. 2.

The conventional copper metal line formation method can have a number ofproblems. One problem may be misalignment. In the process of devicefeature or pattern exposure, the alignment between successive layersthat are being created is of critical importance. Smaller devicedimensions place even more stringent requirements on the accuracy of thealignment of the successive layers that are superimposed on each other.In FIG. 2, following the etching of the conductive layer 58 in which thephotoresist layer 60 is used as a mask to form conductive lines 58, viarecesses VR may be formed at the juncture of a conductive line 58 andthe hard mask 56 and/or the dielectric layer 54. Via recesses can becaused when the photoresist layer is misaligned (e.g., shifted to oneside). Such misalignment can result from a mask misalignment failure,for example, during the photolithography process. Due to thismisalignment, the via recess formed can be a serious problem in theconventional copper etch approach by causing unstable yield anddecreased reliability.

BRIEF DESCRIPTION OF DRAWINGS

Embodiments of the present disclosure are best understood from thefollowing detailed description when read with the accompanying figures.It is emphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIGS. 1 and 2 are cross-sectional views of a part of an interconnectstructure of a semiconductor device from the prior art.

FIG. 3 is a flowchart of a method of fabricating an interconnectstructure of a semiconductor device according to various embodiments ofthe present disclosure.

FIGS. 4-12 are diagrammatic fragmentary cross-sectional side views of aportion of a wafer at various stages of fabrication in accordance withvarious embodiments of the present disclosure.

DETAILED DESCRIPTION

In the following description, specific details are set forth to providea thorough understanding of embodiments of the present disclosure.However, one having ordinary skill in the art will recognize thatembodiments of the disclosure can be practiced without these specificdetails. In some instances, well-known structures and processes are notdescribed in detail to avoid unnecessarily obscuring embodiments of thepresent disclosure.

Embodiments will be described with respect to a specific context, namelyan interconnect structure for an integrated circuit. Other embodimentsmay also be applied, however, to other semiconductor devices andfeatures. For instance, the present teachings could be applied tostructures other than an integrated circuit, such as an interposerdevice, a printed circuit board, a package substrate, and the like.

With reference now to FIG. 3, there is shown a flowchart of a method 2for fabricating an interconnect structure of a semiconductor deviceaccording to various aspects of the present disclosure. Referring toFIG. 3, the method 2 includes block 4, in which a dielectric layer isformed on a substrate. The method 2 includes block 6, in which thedielectric layer is patterned to form an opening therein. The method 2includes block 8, in which the opening is filled and the dielectriclayer is covered with a metal layer. The method 2 includes block 10, inwhich the metal layer is planarized so that the metal layer is co-planarwith a top of the dielectric layer. The method 2 includes block 12, inwhich a treating process is performed on the metal layer to convert atop surface thereof into a metal oxide layer, the metal oxide layerhaving a predetermined thickness. The method 2 includes block 14, inwhich a copper-containing layer is formed over the metal oxide layer andthe dielectric layer. The method 2 includes block 16, in which thecopper-containing layer is etched to form interconnect features. Theetching stops at the metal oxide layer and does not etch into theunderlying metal layer. The method 2 further includes block 18, in whicha radiation exposure process is performed on the metal oxide layer toconvert the metal oxide layer into a non-oxidized metal layer.

It is understood that additional processes may be performed before,during, or after the blocks 4-18 shown in FIG. 3 to complete thefabrication of the semiconductor device, but these additional processesare not discussed herein in detail for the sake of simplicity.

FIGS. 4-12 are diagrammatic fragmentary cross-sectional side views of aportion of a wafer at various fabrication stages according toembodiments of the method 2 of FIG. 3. It is understood that FIGS. 4-12have been simplified for a better understanding of the inventiveconcepts of the present disclosure. It should be appreciated that thematerials, geometries, dimensions, structures, and process parametersdescribed herein are exemplary only, and are not intended to be, andshould not be construed to be, limiting to the invention claimed herein.Many alternatives and modifications will be apparent to those skilled inthe art, once informed by the present disclosure.

With reference now to FIG. 4, there is shown an illustrativesemiconductor structure 100 shown in highly simplified cross-sectionalviews. Various features not necessary for understanding of the inventionhave been omitted for sake of clarity and brevity. Semiconductorstructure 100 includes a substrate 110 upon which has been formed anetch stop layer 120. Substrate 110 refers generally to any structures ormaterials underlying etch stop layer 120. In some applications,substrate 110 includes a semiconductor wafer such as a bulk siliconwafer or a silicon (or other semiconductor material) layer formed atop abulk wafer and separated therefrom by, e.g., a buried oxide layer in aso-called silicon on insulator (SOI) arrangement. One or more active orpassive devices, such as transistors or capacitors, could be formed insubstrate 110. In another application, substrate 110 could be anunderlying metal (or other conductor) layer in a multi-metalinterconnect scheme. For instance, substrate 110 could be an underlyingmetal layer (or several stacked metal layers) manufactured according tothe steps illustrated in FIGS. 4-12.

A dielectric layer 130, preferably a low-k dielectric layer 130 isformed on the etch stop layer 120. Low k generally refers to adielectric layer having a dielectric constant of less than about 3.5.Materials such as porous silicon oxide, doped silicon oxide, siliconcarbide, silicon oxynitride, and the like could be employed fordielectric layer 130, although these are examples only and are notintended to be exhaustive or limiting. The dielectric layer 130 may beformed on the etch stop layer 120 by a process such as, for examplevapor deposition, plasma-enhanced chemical vapor deposition, spin oncoating, or other like processes.

Hard mask 140 is formed atop dielectric layer 130. In a case wheredielectric layer 130 is an oxide, hard mask 140 could be, for example,silicon nitride or another material that has a high degree of resistanceto etchants typically employed to etch oxides. Other materials, such asSiCN, SiOC, and the like could also be employed for hard mask 140.

Mask 150 is formed atop hard mask 140. In the illustrated embodiment,mask 150 is a tri-layer mask comprising three separate layers. While aconventional mask layer, such as a single polymer photoresist layer,could be employed, a tri-layer mask 150 allows for the formation offiner features having smaller dimensions and pitch. In the illustratedembodiment, bottom layer 160 of tri-layer mask 150 is a carbon organiclayer, similar to a conventional photoresist layer. Middle layer 170 isa silicon containing carbon film, employed to help pattern bottom layer160. Top layer 180 is a photoresist material, such as for instance, aphotoresist material designed for exposure to 193 nm wavelengths, andpreferably designed for immersion photolithography, for instance.

As shown in FIG. 4, an opening 190 is formed in mask 150, using knownlithography techniques, such as for instance, immersionphotolithography. This opening will be transferred to all layers of mask150, through hard mask 140 and then to dielectric layer 130 and etchstop layer 120, resulting in an opening 195, sometimes referred toherein as a via opening, being formed in dielectric layer 130 and etchstop layer 120, as shown in FIG. 5. Note that opening 195 exposes anunderlying portion of substrate 110 which, as described above, could bean underlying conductive interconnect, a transistor contact, or thelike. Mask 150 is removed using known ashing and/or etching techniques,the details of which are omitted herein.

Turning now to FIG. 6, a metal layer 200 is deposited over semiconductorstructure 100. In illustrated embodiments, a material of the metal layer200 is a copper alloy. Examples of a suitable copper alloy include CuMn,CuCr, CuV, CuNb, and CuTi. The copper alloy may be in the range of fromabout 90% copper to about 99.8% copper. Other suitable alloys andpercentages will be apparent to those skilled in the art uponundertaking routine experimentation once informed by the presentdisclosure. By using a copper alloy material, it is possible tomanufacture copper interconnects without the need to form barrier lines,such as Ta, TaN, and the like, that are commonly employed inconventional damascene processes. That being said, it is within thecontemplated scope of the present invention that a barrier liner couldbe employed in some applications.

In one embodiment, metal layer 200 is formed by a plasma vapordeposition (PVD) that completely fills opening 195 and forms a blanketcoating over a top surface of dielectric layer 130, or more accuratelyover the top surface of hard mask 140 overlying dielectric layer 130. Insome embodiments, hard mask 140 may be omitted, in which case metallayer 200 would be formed on dielectric layer 130. Metal layer 200 maybe formed to a thickness above dielectric layer 130 of from about 500 Ato about 2 um, depending upon the desired application and the technologynode employed.

In another embodiment, metal layer 200 is formed by first depositing aseed layer by, e.g., physical vapor deposition techniques. The seedlayer could be formed to a thickness of perhaps about 20 A to about 100A, although other thicknesses could be employed depending upon theapplication and the desired process. Then a copper alloy material isformed on the seed layer using, e.g., an electro-plating or electro-lessplating technique. The metal layer 200 maybe deposited by still otherprocesses, such as CVD, ALD, sputtering, and spin-on coating.

The metal layer 200 and, in some embodiments the hard mask layer 140 areplanarized by a chemical mechanical polishing (CMP) or an etch backstep, for example so that a top of the metal layer 200 is substantiallyco-planar with a top surface of the dielectric layer 130, as illustratedin FIG. 7. As shown in FIG. 8, in an aspect of the present disclosure, atreatment process such as an anneal, plasma or heat process 210 isapplied to the semiconductor structure 100 to convert a top surface ofthe metal layer 200 into a metal oxide layer 201. The anneal process 210may be a rapid thermal anneal (RTA), a laser anneal, and/or a flash lampanneal. The anneal process may be conducted in an oxygen ambient, acarbon dioxide ambient, or a combination of steam ambient and oxygenambient combined. The annealing may be performed in a single wafer rapidthermal annealing (RTP) system or a batch type furnace system or theanneal procedure can be performed in situ in the same tool. In anexemplary embodiment, the anneal process 210 is performed in an oxygenor a carbon dioxide atmosphere and the semiconductor substrate 100 isannealed at a temperature range from about 25 C to about 400 C for atime from about 1 second to about 600 seconds. As a result of thesemiconductor substrate 100 being annealed in an oxygen atmosphere, atop surface of the metal layer 200 is converted into the metal oxidelayer 201. In one embodiment, the metal oxide layer 201 is a copperoxide layer, although other metal oxides may be produced depending uponthe desired application and the technology node employed. In oneembodiment, the metal oxide layer 201 has a thickness of from about 10Angstroms to about 200 Angstroms, although other oxide layer thicknessescan be achieved depending on the tailoring of the anneal process 210. Insome embodiments, the metal oxide layer 201 is substantiallynon-conductive.

Referring now to FIG. 9, a copper containing layer 220 is deposited overthe metal oxide layer 201 and the dielectric layer 130. The coppercontaining layer 220 may be deposited by plasma vapor deposition (PVD),for example. In some embodiments, the copper containing layer 220 isthereafter thinned down (e.g., via chemical mechanical polish, CMP, byetch back, or the like). Although not shown in FIG. 9, in someembodiments a barrier layer may be formed on the dielectric layer 130and the metal oxide layer 201 prior to forming the copper containinglayer 220 over the dielectric layer 130 and the metal oxide layer 201.

Also not shown in FIG. 9, an etch stop layer may be formed on theplanarized copper containing layer 220. In one embodiment, the etch stoplayer is formed of silicon nitride, silicon carbon nitride, or anothermaterial that provides sufficient etch selectivity relative to thecopper containing layer 220.

Turning now to FIG. 10, a second mask 230 is formed. In the illustratedexample, mask 230 is a tri-layer mask similar to mask 150 illustrated inFIG. 4. As with the previously described steps, it is not necessary touse a tri-layer mask, unless the particular application and feature sizecalls for such an approach. Regardless of the type of mask employed, apattern is formed in mask 230 as shown in FIG. 10. Next, as shown inFIG. 11, the pattern is transferred to copper containing layer 220 usingknown lithography techniques. Copper containing layer 220 is preferablyetched anisotropically to form nearly vertical sidewalls. In someembodiments, a chlorine plasma etch is employed to pattern coppercontaining layer 220. Other plasma etches, including reactive ionetching (RIE), could also be employed.

The result of the etching step is that the copper containing layer 220is patterned into interconnect features or interconnects 280. Theseinterconnect features 280 run across the major surface of semiconductorstructure 100 and may be metal lines, metal vias, or via features toprovide vertical electrical routing between metal lines. The etchingstops at the metal oxide layer 201 and does not etch thereunder, thusavoiding undesirable recesses that may be formed in the prior art methodand resulting in a recess free (RF) semiconductor structure 100. Thefaster etching rate of the copper containing layer 220 is desirablebecause it eliminates or reduces the amount of undercutting that willoccur in the metal oxide layer 201. As can be seen from FIG. 11, thereis little or no undercutting of the metal oxide layer 201.

Referring now to FIG. 12, a radiation exposure process 300 performed bya lithography exposing tool is applied to the semiconductor structure100 to convert the metal oxide layer 201 substantially into anon-oxidized metal layer 310. The exposing tool may utilize a deepultraviolet (DUV), extreme ultraviolet (EUV), or X-ray radiation. In anexemplary embodiment where X-ray radiation is used, the X-ray exposureprocess is performed in an inert, reduction or oxygen-free atmosphere,at an X-ray wavelength from about 10-9 to about 10-12 m, at an energyfrom about 1 eV to about 10 GeV, at a temperature range from about 25 Cto about 400 C, and for a time from about 1 second to about 600 seconds.When the radiation exposure process 300 projects onto the metal oxidelayer 201, it induces CuO, Cu₂O, Mn₂O₃, Mn₃O₄, MnO₂, Cr₂O₃, V₂O₃, orTiO₂, and results in converting the oxidized metal layer 201substantially into the non-oxidized metal layer 310. In one embodiment,the non-oxidized metal layer 310 is substantially conductive in orderfor the metal layer 200 to be conductive to other conductive layerstherearound.

Further processing steps could include depositing a dielectric layer inthe openings between the interconnect features 280 and planarizing thedielectric layer. The above described process steps may be repeated forthe formation of additional vertical and horizontal interconnectfeatures.

Although the present embodiments and their advantages have beendescribed in detail, it should be understood that various changes,substitutions, and alterations can be made herein without departing fromthe scope of the disclosure as defined by the appended claims.

The present disclosure has described various exemplary embodiments.According to one embodiment, a method for forming a semiconductorinterconnect structure includes forming a dielectric layer on asubstrate and patterning the dielectric layer to form an openingtherein. A metal layer fills the opening and covers the dielectriclayer. The metal layer is planarized so that it is co-planar with a topof the dielectric layer. A treating process is performed on the metallayer to convert a top surface thereof into a metal oxide layer. Acopper-containing layer is then formed over the metal oxide layer andthe dielectric layer. The copper-containing layer is etched to forminterconnect features, wherein the etching stops at the metal oxidelayer and does not etch into the underlying metal layer. A radiationexposure process is thereafter performed on the metal oxide layer toconvert it into a non-oxidized metal layer.

According to another embodiment, a method for forming an integratedcircuit interconnect structure includes forming a via opening in adielectric layer on a substrate. A copper alloy layer fills the viaopening and covers the dielectric layer. The copper alloy layer isplanarized so that the copper alloy layer is co-planar with a top of thedielectric layer. The copper alloy layer is annealed to convert a topsurface thereof into a copper alloy oxide layer. A copper-containinglayer is formed over the copper alloy oxide layer and the dielectriclayer. The copper-containing layer is etched to form interconnectfeatures, wherein the etching stops substantially at the copper alloyoxide layer and does not etch into the underlying copper alloy layer. Aradiation treatment is performed on the copper alloy oxide layer toconvert the copper alloy oxide layer into a non-oxidized copper alloylayer.

In the preceding detailed description, specific exemplary embodimentshave been described. It will, however, be apparent to a person ofordinary skill in the art that various modifications, structures,processes, and changes may be made thereto without departing from thebroader spirit and scope of the present disclosure. The specificationand drawings are, accordingly, to be regarded as illustrative and notrestrictive. It is understood that embodiments of the present disclosureare capable of using various other combinations and environments and arecapable of changes or modifications within the scope of the claims.

What is claimed is:
 1. A method for forming a semiconductor interconnectstructure, comprising: forming a patterned metal layer on a substrate;performing a treating process on the metal layer to convert a topsurface thereof into a metal oxide layer, the metal oxide layer having apredetermined thickness; forming a metal-containing layer over the metaloxide layer; etching the metal-containing layer to form interconnectfeatures; and performing a radiation exposure process on the metal oxidelayer to convert the metal oxide layer into a non-oxidized metal layer.2. The method of claim 1, wherein the step of forming a patterned metallayer on a substrate comprises: forming a dielectric layer on thesubstrate; forming a hard mask layer on the dielectric layer; forming atri-layer mask layer on the hard mask layer; patterning the tri-layermask layer to form an opening therein; forming an opening in the hardmask layer using the opening in the tri-layer mask layer as a pattern;forming an opening in the dielectric layer using the opening in the hardmask layer as a pattern; filling the opening in the dielectric layerwith the metal layer; and patterning the metal layer.
 3. The method ofclaim 1, wherein the patterned metal layer is a copper alloy.
 4. Themethod of claim 1, wherein the patterned metal layer is a materialselected from the group consisting of CuMn, CuCr, CuV, CuNb, CuTi, andcombinations thereof.
 5. The method of claim 1, wherein themetal-containing layer is a copper alloy.
 6. The method of claim 1,wherein the step of performing a treating process includes a processselected from the group consisting of a plasma process, an annealprocess, a heat process, a rapid thermal anneal process, a laser anneal,a flash lamp anneal, and combinations thereof.
 7. The method of claim 1,wherein the step of performing a treating process includes performingthe treating process in an oxygen atmosphere.
 8. The method of claim 1,wherein the step of performing a radiation exposure process includesexposing the metal oxide layer to radiation selected from the groupconsisting of deep ultraviolet, extreme ultraviolet, X-ray, andcombinations thereof.
 9. A method for forming a semiconductorinterconnect structure, comprising: forming a dielectric layer on asubstrate; patterning the dielectric layer to form an opening in thedielectric layer; filling the opening and covering the dielectric layerwith a conductive layer; planarizing the conductive layer so that theconductive layer is co-planar with a top of the dielectric layer;performing a treating process on the conductive layer to convert a topsurface thereof into a non-conductive sub-layer; forming a secondconductive layer on the non-conductive sub-layer and the dielectriclayer; etching the second conductive layer to form interconnectfeatures; and performing a radiation exposure process on thenon-conductive sub-layer to convert the non-conductive sub-layer into aconductive sub-layer.
 10. The method of claim 9, wherein the conductivelayer is a copper alloy and wherein the non-conductive sub-layer iscopper oxide.
 11. The method of claim 9, wherein the second conductivelayer and the conductive layer comprise the same material.
 12. Themethod of claim 9, wherein the step of patterning the dielectric layerincludes: forming a hard mask over the dielectric layer; forming atri-layer mask over the hard mask; patterning the tri-layer mask;patterning the hard mask using the patterned tri-layer mask as apattern; and patterning the dielectric layer using the patterned hardmask as a pattern.
 13. The method of claim 12, wherein the tri-layermask includes a bottom layer comprising a carbon organic layer, a middlelayer comprising a silicon containing carbon film, and a top layercomprising a photoresist material.
 14. The method of claim 9, whereinthe step of performing a treating process on the conductive layer toconvert a top surface thereof into a non-conductive sub-layer includesexposing the structure to a process selected from the group consistingof a plasma process and a heat process, and combinations thereof, in anatmosphere selected from the group consisting of an oxygen atmosphere, acarbon dioxide atmosphere, a combined steam and oxygen ambient, andcombinations thereof.
 15. The method of claim 9, wherein the step ofetching the second conductive layer to form interconnect featuresincludes exposing the structure to a chlorine plasma.
 16. A method forforming a semiconductor interconnect structure, comprising: forming apatterned copper alloy layer on a substrate; converting a top surface ofthe a patterned copper alloy layer into a metal oxide layer; forming acopper-containing layer over the metal oxide layer; patterning thecopper-containing layer; and converting the metal oxide layer back intoa copper alloy layer after patterning the copper-containing layer. 17.The method of claim 16, wherein the step of converting a top surface ofthe a patterned copper alloy layer into a metal oxide layer includesperforming an anneal process on the patterned copper alloy layer in anatmosphere selected from the group consisting of oxygen ambient, carbondioxide ambient, combination steam ambient and oxygen ambient, andcombinations thereof.
 18. The method of claim 16, wherein the step ofconverting a top surface of the a patterned copper alloy layer into ametal oxide layer results in a metal oxide layer having a thickness offrom about 10 Å to about 200 Å.
 19. The method of claim 16, wherein thestep of patterning the copper-containing layer includes exposing thestructure to an etchant that etches copper without undercutting themetal oxide layer.
 20. The method of claim 19, wherein the etchantincludes chlorine.